This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-212590, filed Jul. 12, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a word drive line reset circuit of a type in which a potential of the word drive line through which a word line drive voltage is supplied is reset in two stages, and it is used, for example, in a DRAM (dynamic random access memory) employing NWR (negative word line reset) system.
2. Description of the Related Art
In a DRAM, it is preferred to decrease the current consumption by maintaining the cut-off current (Ioff) of a memory cell transistor at low level, and also to cope with the trend of higher operating speed and lower supply voltage by lowering the threshold voltage of a memory cell transistor.
To satisfy such contradictory demands, hitherto, the gate oxide film of the memory cell transistor has been improved to have a high breakdown voltage and the gate film thickness has been thinned, and using the improved S-factor of the memory cell transistor, a low threshold voltage was maintained while keeping the Ioff at low level.
However, as the DRAM becomes finer and the supply voltage is further lowered, it is becoming hard to satisfy the contradictory requirements of low level of Ioff and low threshold voltage of the memory cell transistor. For example, since the electric field (Eox) applied to the gate oxide film is 6 MV/cm or more at the present, the conventional technique is beyond the limit.
To solve this problem, the NWR system has been proposed. In the NWR system, the resetting potential of the word line is set at a negative potential (Vnn), the gate-source voltage Vgs when the memory cell transistor is off is set at a negative value (Vgs less than 0), and therefore both low Ioff level and low threshold voltage are realized.
Here is discussed the amount Q of electric charge flowing into a power supply line Vnn in the resetting operation of the word line. The electric charge amount Q, as expressed in formula Q=CV, is expressed by the product of capacity C and potential difference V.
First considering the capacity, the word lines are connected to gate electrodes of a plurality of memory cells, and have the coupling capacity with bit lines and memory cell capacitors, and hence the capacity is large. Word drive lines are shared by a plurality of row decoders, and hence the capacity is also relatively large.
As for the potential difference, a boosting potential (Vpp) is generally used as the setting potential of the word lines in order to write xe2x80x9cHxe2x80x9d level data in the memory cell. Accordingly, since the electric charge amount Q is expressed by the product of capacity C and potential difference V as described above, then when resetting the word line, the voltage swing Vpp-Vnn is large. Therefore, in resetting operation of the word line, the amount of electric charge flowing into the power supply line Vnn is very large. As a result, a large current flows into the power supply line Vnn in a relatively short time.
Vnn is generally produced in a chip by means of a charge pump circuit, and supplied to the necessary circuits in the chip via the power supply line Vnn composed of metal wiring or the like. The charge pump circuit is generally high in output impedance. Thus, when a large current flows into the power supply line Vnn in a relatively short time, the potential of the power supply line Vnn locally rises, which is known as a power supply bounce.
Since the word line in an inactivated state is electrically connected to a Vnn power supply line, the potential of the inactivated word line is boosted by this power supply bounce, and the electric charge accumulated in the memory cell may leak.
To suppress the power supply bounce, it may be attempted to provide a plenty of stabilizing capacitors for Vnn near the row decoders, or decrease the RC product of the power supply line wiring (decrease the resistance of wiring material, decrease the dielectric constant of insulating material, or increase the width of power supply wiring).
In the former case, however, the problem is the increase of chip area, and hence it is not realistic to provide stabilizing capacitors for Vnn in the core circuit. In the latter case, improvement or modification of wiring material and insulation film material may lead to increase in the cost of development, increase in the period of development, and increase in the necessary chip area. Also in the latter case, if low RC product of wiring material is realized, a large capacity is needed in the charge pump circuit for generating Vnn, rendering the necessary chip area large.
To suppress the power supply bounce of the power supply line of such negative potential (Vnn) and to reduce the load to the negative potential generating circuit, for example, as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2000-36191, a method of resetting by dividing the word line potential of DRAM in two stages is proposed (known as t within wo-stage resetting method). In this two-stage resetting method, when resetting the word lines, the potential of the word lines and the word drive lines is first set at the grounding potential (Vss), and then set at Vnn, so that an electric current flown into the Vnn power supply line may be decreased than conventional.
FIG. 5A is a block diagram of an example of connectional relation between a word drive line drive circuit and a plurality of row decoders in a conventional DRAM with the two stage reset system. In FIG. 5A, the word drive line drive circuit resets the word drive line potential in two stages, and thus resets the word line potential in two stages.
In FIG. 5A, a word drive line drive circuit (WDRV DRV) 41 is provided in each unit block of a memory cell array, that is, in every sub array (not shown). A block select signal BlockSel for selecting the sub array and a row address signal Addr for specifying a selection line within the sub array are inputted to the word drive line drive circuit (WDRV DRV) 41. Also, a first reset control signal Reset less than 0 greater than  and a second reset control signal Reset less than 1 greater than  are inputted to the word drive line drive circuit (WDRV DRV) 41.
A plurality of sub row decoders (SRD#0, SRD#1, . . . , SRD#n) 420 to 420n are provided corresponding to a plurality of sub word lines SWL less than 0 greater than , SWL less than 1), . . . , SWL less than n greater than  in every sub array. A word drive voltage is supplied from the word drive line drive circuit 41 through first word drive line wdrv_p to the sub row decoders (SRD#0, SRD#1, . . . , SRD∩n) 420 to 420n, and a word drive signal is supplied from the word drive line drive circuit 41 through second word drive line wdrv_n to the sub row decoders (SRD#0, SRD#1, . . . , SRD#n) 420 to 420n. Also, the sub row decoders (SRD#0, SRD#1, . . . , SRD#n) 420 to 420n receive and decode an address signal MWL for specifying a selection sub word line (a row address input other than the row address signal Addr for specifying the selection line within the sub array) to selectively drive a corresponding sub word line SWL less than 0 greater than , SWL less than 1 greater than , . . . , SWL less than n greater than .
A delay circuit (Delay) 43 receives the first reset control signal Reset less than 0 greater than , and produces the second reset control signal Reset less than 1 greater than .
FIG. 5B is a signal chart showing the timing relation between the reset control signal Reset less than 0 greater than  and the reset control signal Reset less than 1 greater than  in the block diagram in FIG. 5A.
FIG. 6 is a circuit diagram of the word drive line drive circuit 41 in FIG. 5A.
In FIG. 6, reference numeral 51 is a decoding circuit, 52 is a dynamic latch circuit, 53 is a level shifting circuit, 54 is a first word drive line drive circuit, and 55 is a second word drive line drive circuit. Further, Vii is a power supply voltage (for example, an internal power supply voltage down-converted from an external power supply voltage in a DRAM), Vpp is a boosted power supply voltage boosted within a DRAM, Vnn is a negative voltage, and Vss is the ground potential.
The first word drive line control circuit 54 comprises a PMOS (P-channel MOS) transistor P1 for driving word drive lines, two NMOS (N-channel MOS) transistors N0, N1, and an NMOS transistor N2. The PMOS transistor P1 for driving word drive lines is driven by an output signal of the level shifting circuit 53 and outputs a word drive voltage to the first word drive line wdrv_p. The two NMOS transistors N0, N1 are connected in series between the drain of the PMOS transistor P1 (connection node of the first word drive line wdrv_p) and Vss node. The NMOS transistor N2 is connected between the source of the NMOS transistor N0 and Vnn node.
The second word drive line control circuit 55 receives a signal of output node A (node A) of the latch circuit 52, and outputs a word drive signal to the second word drive line wdrv_n.
FIG. 7 is a circuit diagram cited for explaining the principle of two-stage resetting operation in the circuit in FIG. 6. FIG. 7 shows a circuit comprising part of the first word drive line control circuit 54, one sub row decoder SRD connected to the first word drive line wdrv_p, one sub word line SWL connected to the sub row decoder SRD, and memory cells MC.
The sub row decoder SRD comprises a PMOS transistor P2 for driving word lines, NMOS transistor N3 for word line potential pull-down, and an NMOS transistor N4 for noise killer. The word line driving PMOS transistor P2 has the source connected to the first word drive line wdrv_p and the drain connected to the sub word line SWL, and receives a word line select signal MWL at the gate. The word line potential pull-down NMOS transistor N3 has the drain connected to the sub word line SWL and the source connected to the Vnn node, and receives the MWL at the gate. The noise killer NMOS transistor N4 is connected parallel to the NMOS transistor N3 and receives the word drive signal at the gate from wdrv_n.
FIG. 8 is a signal chart of an example of two-stage resetting operation in the circuit in FIG. 7.
First, when resetting the wdrv_p, the output Set of the level shifting circuit 53 is xe2x80x9cLxe2x80x9d level, and the PMOS transistor P1 in the first word drive line control circuit 54 is turned on, and the wdrv_p becomes xe2x80x9cHxe2x80x9d level. At this time, the resetting NMOS transistors N1 and N2 are in off state. At this time, the wdrv_n is xe2x80x9cLxe2x80x9d level.
Next, when resetting the wdrv_p, first the output Set of the level shifting circuit 53 becomes xe2x80x9cHxe2x80x9d level, and the PMOS transistor P1 in the first word drive line control circuit 54 is turned off.
Consequently, the reset control signal Reset less than 0 greater than  becomes xe2x80x9cHxe2x80x9d level for a short time, and the resetting NMOS transistor N1 is turned on for a short time, so that the electric charge of wdrv_p is discharged in Vss node. As a result, the resetting NMOS transistor N2 is turned on, and the charge of wdrv_p is discharged in Vnn node. At this time, the wdrv_n is xe2x80x9cHxe2x80x9d level, and the noise killer NMOS transistor N4 in the sub row decoder SRD is turned on, and the charge of wdrv_n is discharged to Vnn node.
By such two-stage resetting operation, the amount of electric charge flowing from the word drive line into the Vnn node is decreased, and the bounce of the Vnn supply line is suppressed.
In such two-stage resetting method, however, since resetting operation of the word drive line is executed twice as mentioned above, control lines are required for both the circuit for connecting the word drive line to Vss and the circuit for connecting the word drive line to Vnn. To determine the second resetting operation timing (that is, the timing of changing over the word drive line from connection with Vss to connection with Vnn), hitherto, the delay circuit (Delay) 43 (FIG. 5A) for delaying the reset control signal by a predetermined time, or the timing generation circuit (not shown) for determining the reset operation timing by monitoring the potential of the word drive line is shared by reset circuits of word drive lines. These circuits are, however, relatively large in the pattern area, and it is difficult to arrange these circuits on a core portion having little extra space in layout region, and thus the word drive line drive circuit can be disposed only in the peripheral portion of the core portion. Accordingly, a fluctuation occurs in the RC delay of each control line wired from the peripheral portion of the core to each reset circuit, and it is hard to set the operation timing of each reset circuit at high precision.
Thus, in the conventional circuit for resetting the word drive line potential in two stages, the layout area on the memory chip is relatively large, and it is hard to set the operation timing of each reset circuit at high precision.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising at least one memory cell array in which a plurality of word lines and a plurality of bit lines intersect with each other, including a plurality of memory cells to be selected by the word lines and the bit lines; a word drive line drive circuit which decodes one part of an address signal, and outputs a word drive voltage to a first word drive line; and
a plurality of row decoders which are provided corresponding to the plurality of word lines in the memory cell array and supplied with a word drive control signal from the first word drive line, and decode other part than the one part of the address signal to selectively drive a corresponding word line, wherein the word drive line drive circuit comprises a decoding circuit which decodes the one part of the address signal; a latch circuit which latches the decode output of the decoding circuit, and receives a reset control signal for controlling the reset start timing of the first word drive line to reset the decode output of the decoding circuit; a first word drive line control circuit which supplies a word drive voltage corresponding to the decode output of the decoding circuit to the first word drive line, and has a first reset circuit connected between the first word drive line and a first potential node to reset the first word drive line to a first potential when a first control signal is activated and a second reset circuit connected between the first word drive line and a second potential node to reset the first word drive line to a second potential when a second control signal is activated; and a two-stage reset control circuit which controls changeover from the activated state of the first control signal to the activated state of the second control signal on the basis of the potential of the first word drive line to change the potential of the first word drive line in two stages including a first stage of the first potential and a second stage of the second potential.